View ISL22326WFV14Z_8833743.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 fn6176.3 caution: these devices are sensitive to electrostatic discharge ; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) and xdcp are registered trademarks of int ersil americas llc. copyright intersil americas llc. 2006, 2008, 2009, 2015. all ri ghts reserved all other trademarks mentioned are the property of their respec tive owners. isl22326 dual digitally controlled potentiometers (xdcp?) low noise, low power, i 2 c ? bus, 128 taps the isl22326 integrates two digitally controlled potentiometers (xdcp) and non-volatile memor y on a monolithic cmos integrated circuit. the digitally controlled potenti ometers are implemented with a combination of resistor elements and cmos switches. the position of the wipers are controlled by the user through the i 2 c bus interface. each potent iometer has an associated volatile wiper register (wr) and a non-volatile initial value register (ivr) that can be directly written to and read by the user. the contents of the wr c ontrols the position of the wiper. at power-up the device recalls the contents of the two dcps ivr to the corresponding wrs. the dcps can be used as three- terminal potentiometers or as two-terminal vari able resistors in a wide variety of applications including control, parameter adjustments, and signal processing. features ? two potentiometers in one package ? 128 resistor taps ?i 2 c serial interface - three address pins, up to eight devices/bus ? non-volatile storage of wiper position ? wiper resistance: 70 ? typical @ v cc = 3.3v ? shutdown mode ? shutdown current 5a max ? power supply: 2.7v to 5.5v ?50k ?? or 10k ? total resistance ? high reliability - endurance: 1,000,000 data c hanges per bit per register - register data retention: 50 years @ t < +55 c ? 14 ld tssop or 16 ld qfn package ? pb-free (rohs compliant) pinouts isl22326 (14 ld tssop) top view isl22326 (16 ld qfn) top view a2 1 2 3 4 5 6 7 sda scl 8 9 10 14 13 12 11 shdn rw0 rl0 rh0 a1 v cc rw1 rl1 rh1 a0 gnd a2 nc nc rw1 scl sda v cc shdn a1 gnd rh1 rl0 rl1 a0 rh0 rw0 1 3 4 15 16 14 13 2 12 10 9 11 6 578 data sheet september 9, 2015
2 fn6176.3 september 9, 2015 block diagram ordering information part number (note) part marking resistance option (k ? ) temp. range (c) package (rohs compliant) pkg. dwg. # isl22326ufv14z* (no longer available, recommended replacement: isl22326wfr16z-tk) 22326 ufvz 50 -40 to +125 14 ld tssop m14.173 isl22326ufr16z* (no longer available, recommended replacement: isl22326wfr16z-tk) 223 26ufz 50 -40 to +125 16 ld 4x4 qfn l16.4x4a ISL22326WFV14Z* 22326 wfvz 10 -40 to +125 14 ld tssop m14.173 isl22326wfr16z* 223 26wfz 10 -40 to +125 16 ld 4x4 qfn l16.4x4a *add -tk suffix for tape and reel. please refer to tb347 for details on reel specifications. note: these intersil pb-free plastic packaged products employ sp ecial pb-free material sets, molding compounds/die attach mater ials, and 100% matte tin plate plus anneal (e3 termination finish, which is ro hs compliant and compatible with both snpb and pb-free solderin g operations). intersil pb-free products are msl classified at pb-free peak re flow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. i 2 c interface v cc rh0 rh1 gnd rl0 rl1 rw0 rw1 scl sda a0 a1 a2 wr1 wr0 shdn power-up interface, control and status logic non- volatile registers isl22326
3 fn6176.3 september 9, 2015 pin descriptions tssop pin number qfn pin number pin name description 115v cc power supply pin 2 16 shdn shutdown active low input 3 1 rh0 high terminal of dcp0 4 2 rl0 low terminal of dcp0 5 3 rw0 wiper terminal of dcp0 6 5 a2 device address input for the i 2 c interface 7 6 scl open drain i 2 c interface clock input 8 7 sda open drain serial data i/o for the i 2 c interface 9 8 gnd device ground pin 10 10 rw1 wiper terminal of dcp1 11 11 rl1 low terminal of dcp1 12 12 rh1 high terminal of dcp1 13 13 a0 device address input for the i 2 c interface 14 14 a1 device address input for the i 2 c interface 4, 9 nc no connection epad* exposed die pad inte rnally connected to gnd *note: pcb thermal land for qf n epad should be connected to gnd plane or left floating. for more information refer to http://www.intersil.com/data/tb/tb389.pdf isl22326
4 fn6176.3 september 9, 2015 absolute maximum ratings thermal information storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c voltage at any digital interface pin with respect to gnd . . . . . . . . . . . . . . . . . . . . -0.3 v to v cc + 0.3 v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v voltage at any dcp pin with respect to gnd. . . . . . . -0.3v t o v cc i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma latchup (note 3) . . . . . . . . . . . . . . . . . . class ii, l evel b @ +125c esd ratings human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350v thermal resistance (typical, notes 1, 2) ? ja (c/w) ? jc ( c / w ) 14 lead tssop . . . . . . . . . . . . . . . . . . 100 n/a 16 lead qfn . . . . . . . . . . . . . . . . . . . . 40 3.0 maximum junction temperat ure (plastic package). . . . . . . . +1 50c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions temperature range (extended industrial). . . . . . . .-40c to +125c v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v power rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mw wiper current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0ma caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ? ja is measured with the component mounted on a high effective the rmal conductivity test board in free air. see tech brief tb379 for details. 2. for ? jc , the case temp location is the center of the exposed metal p ad on the package underside. 3. jedec class ii pulse conditions and failure criterion used. l evel b exceptions are: using a max positive pulse of 6.5v on th e shdn pin, and using a max negative pulse of -0.8v for all pins. analog specifications over recommended operating condi tions, unless otherwise stated. symbol parameter test conditions min (note 20) typ (note 4) max (note 20) unit r total r h to r l resistance w option 10 k ? u option 50 k ? r h to r l resistance tolerance w and u option -20 +20 % end-to-end temperature coefficient w option 50 ppm/c (note 17) u option 80 ppm/c (note 17) r w wiper resistance v cc = 3.3v, wiper current = v cc /r total 70 200 ? v rh , v rl v rh and v rl terminal voltages v rh and v rl to gnd 0 v cc v c h /c l /c w (note 19) potentiometer capacitance 10/10/25 pf i lkgdcp leakage on dcp pins voltage at pin from gnd to v cc 0.1 1 a voltage divider mode (0v @ r l i; v cc @ r h i; measured at r w i, unloaded; i = 0 or 1) inl (note 9) integral non-linearity monotonic over all tap positions, w and u option -1 1 lsb (note 5) dnl (note 8) differential non-linearity monotoni c over all tap positions, w a nd u option -0.5 0.5 lsb (note 5) zserror (note 6) zero-scale error w option 0 1 5 lsb (note 5) u option 0 0.5 2 fserror (note 7) full-scale error w option -5 -1 0 lsb (note 5) u option -2 -1 0 v match (note 10) dcp to dcp matching any two dcps at same tap position, same voltage at all rh terminals, and same voltage at all rl terminals -2 2 lsb (note 5) tc v (note 11) ratiometric temperature coeffi cient dcp register set to 40 hex 4 ppm/c isl22326
5 fn6176.3 september 9, 2015 resistor mode (measurements between r w i and r l i with r h i not connected, or between r w i and r h i with r l i not connected. i = 0 or 1) rinl (note 15) integral non-linearity dcp register set between 10h and 7fh; monotonic over all tap positions -1 1 mi (note 12) rdnl (note 14) differential non-linearity dcp register set between 10h and 7fh; monotonic over all tap positions, w option -1 1 mi (note 12) dcp register set between 10h and 7fh; monotonic over all tap positions, u option -0.5 0.5 mi (note 12) roffset (note 13) offset w option 0 1 5 mi (note 12) u option 0 0.5 2 mi (note 12) r match (note 16) dcp to dcp matching any two dcps at the same tap position with the same terminal voltages -2 2 mi (note 12) analog specifications over recommended operating condi tions, unless otherwise stated. (continued) symbol parameter test conditions min (note 20) typ (note 4) max (note 20) unit operating specifications over the recommended operating c onditions, unless otherwise spe cified. symbol parameter test conditions min (note 20) typ (note 4) max (note 20) unit i cc1 v cc supply current (volatile write/read) f scl = 400khz; sda = open; (for i 2 c, active, read and write states) 0.5 ma i cc2 v cc supply current (non-volatile write/read) f scl = 400khz; sda = open; (for i 2 c, active, read and write states) 3ma i sb v cc current (standby) v cc = +5.5v @ +85c, i 2 c interface in standby state 5a v cc = +5.5v @ +125c, i 2 c interface in standby state 7a v cc = +3.6v @ +85c, i 2 c interface in standby state 3a v cc = +3.6v @ +125c, i 2 c interface in standby state 5a i sd v cc current (shutdown) v cc = +5.5v @ +85c, i 2 c interface in standby state 3a v cc = +5.5v @ +125c, i 2 c interface in standby state 5a v cc = +3.6v @ +85c, i 2 c interface in standby state 2a v cc = +3.6v @ +125c, i 2 c interface in standby state 4a i lkgdig leakage current, at pins a0, a1, a2, shdn , sda and scl voltage at pin from gnd to v cc -1 1 a t wrt (note 19) dcp wiper response time scl falling edge of last bit of dcp data byte to wiper new position 1.5 s t shdnrec (note 19) dcp recall time from shutdown mode from rising edge of shdn signal to wiper stored position and rh connection 1.5 s scl falling edge of last bit of acr data byte to wiper stored position and rh connection 1.5 s vpor power-on recall voltage minimum v cc at which memory recall occurs 2.0 2.6 v vccramp v cc ramp rate 0.2 v/ms isl22326
6 fn6176.3 september 9, 2015 t d power-up delay v cc above vpor, to dcp initial value register recall completed, and i 2 c interface in standby state 3ms eeprom specification eeprom endurance 1,000,000 cycles eeprom retention temperature t < +55 c 50 years t wc (note 18) non-volatile write cycle time 12 20 ms serial interface specifications v il a2, a1, a0, shdn , sda, and scl input buffer low voltage -0.3 0.3*v cc v v ih a2, a1, a0, shdn , sda, and scl input buffer high voltage 0.7*v cc v cc + 0.3 v hysteresis sda and scl input buffer hysteresis 0.05*v cc v v ol sda output buffer low voltage, sinking 4ma 00.4v cpin (note 19) a2, a1, a0, shdn , sda, and scl pin capacitance 10 pf f scl scl frequency 400 khz t sp pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed 50 ns t aa scl falling edge to sda output data valid scl falling edge crossing 30% of v cc , until sda exits the 30% to 70% of v cc window 900 ns t buf time the bus must be free before the start of a new transmission sda crossing 70% of v cc during a stop condition, to sda crossing 70% of v cc during the following start condition 1300 ns t low clock low time measured at the 30% of v cc crossing 1300 ns t high clock high time measured at the 70% of v cc crossing 600 ns t su:sta start condition setup time scl rising edge to sda falling edge; both crossing 70% of v cc 600 ns t hd:sta start condition hold time from sda falling edge crossing 30% of v cc to scl falling edge crossing 70% of v cc 600 ns t su:dat input data setup time from sda exiting the 30% to 70% of v cc window, to scl rising edge crossing 30% of v cc 100 ns t hd:dat input data hold time from scl rising edge crossing 70% of v cc to sda entering the 30% to 70% of v cc window 0ns t su:sto stop condition setup time from scl rising edge crossing 70% of v cc to sda rising edge crossing 30% of v cc 600 ns t hd:sto stop condition hold time for read, or volatile only write from sda rising edge to scl falling edge; both crossing 70% of v cc 1300 ns t dh output data hold time from scl falling edge crossing 30% of v cc , until sda enters the 30% to 70% of v cc window 0ns t r sda and scl rise time from 30% to 70% of v cc 20 + 0.1*cb 250 ns t f sda and scl fall time from 70% to 30% of v cc 20 + 0.1*cb 250 ns operating specifications over the recommended operating c onditions, unless otherwise spe cified. (continued) symbol parameter test conditions min (note 20) typ (note 4) max (note 20) unit isl22326
7 fn6176.3 september 9, 2015 cb capacitive loading of sda or scl total on-chip and off-chip 10 400 pf rpu sda and scl bus pull-up resistor off-chip maximum is determined by t r and t f for cb = 400pf, max is about 2k ? ~2.5k ? for cb = 40pf, max is about 15k ? ~20k ? 1k ? t su:a a2, a1 and a0 setup time before start condition 600 ns t hd:a a2, a1 and a0 hold time after stop condition 600 ns notes: 4. typical values are for t a = +25c and 3.3v supply voltage 5. lsb: [v(r w ) 127 C v(r w ) 0 ]/127. v(r w ) 127 and v(r w ) 0 are v(r w ) for the dcp register set to 7f hex and 00 hex respectively. l sb is the incremental voltage when changing from one tap to an adjacent t ap. 6. zs error = v(rw) 0 /lsb. 7. fs error = [v(rw) 127 C v cc ]/lsb. 8. dnl = [v(rw) i C v(rw) i-1 ]/lsb-1, for i = 1 to 127. i is the dcp register setting. 9. inl = [v(rw) i C i ? lsb C v(rw) 0 ]/lsb for i = 1 to 127. 10. v match = [v(rwx) i C v(rwy) i ]/lsb, for i = 1 to 127, x = 0 to 1 and y = 0 to 1. 11. for i = 16 to 112 decimal, t = -40c to +125c. max( ) is th e maximum value of the wiper voltage and min ( ) is the minimum value of the wiper voltage o ver the temperature range. 12. mi = | rw 127 C rw 0 | /127. mi is a minimum increment. rw 127 and rw 0 are the measured resistances for the dcp register set to 7f he x and 00 hex respectively. 13. roffset = rw 0 /mi, when measuring between rw and rl. roffset = rw 127 /mi, when measuring between rw and rh. 14. rdnl = (rw i C rw i-1 )/mi -1, for i = 16 to 127. 15. rinl = [rw i C (mi ? i) C rw 0 ]/mi, for i = 16 to 127. 16. r match = (rw i,x C rw i,y ) /mi, for i = 1 to 127, x = 0 to 1 and y = 0 to 1. 17. for i = 16 to 112, t = -40c to +125c. max( ) is the maximu m value of the resistance and min ( ) is the minimum value of the resistance over the temperature range. 18. t wc is the time from a valid stop condition at the end of a write sequence of i 2 c serial interface, to the end of the self-timed internal non-v olatile write cycle. 19. limits should be considered ty pical and are not production t ested. 20. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. operating specifications over the recommended operating c onditions, unless otherwise spe cified. (continued) symbol parameter test conditions min (note 20) typ (note 4) max (note 20) unit tc v max v rw ?? i ?? min v rw ?? i ?? C max v rw ?? i ?? min v rw ?? i ?? + ?? 2 ? --------------------------------------------------------------- ------------------------------ - 10 6 +165c -------------------- - ? = tc r max ri ?? min ri ?? C ?? max ri ?? min ri ?? + ?? 2 ? --------------------------------------------------------------- - 10 6 +165c -------------------- - ? = isl22326
8 fn6176.3 september 9, 2015 sda vs scl timing a0, a1, and a2 pin timing [ t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda (input timing) sda (output timing) t f t low t buf t aa t r t sp t hd:sto t hd:a scl sda a0, a1, or a2 t su:a clk 1 start stop typical performance curves figure 1. wiper resistance vs tap position [ i(rw) = v cc /r total ] for 10k ? (w) figure 2. standby i cc vs v cc 0 10 20 30 40 50 60 70 80 90 100 020406080100120 tap position (decimal) v cc = 3.3v, t = +125c v cc = 3.3v, t = +20c v cc = 3.3v, t = -40c wiper resisitance ( ? ) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 2.7 3.2 3.7 4.2 4.7 5.2 v cc (v) i sb (a) t = +25c t = +125c isl22326
9 fn6176.3 september 9, 2015 figure 3. dnl vs tap position in voltage divider mode for 10k ? (w) figure 4. inl vs tap position in voltage divider mode for 10k ? (w) figure 5. zs error vs temperature figure 6. fs error vs temperature figure 7. dnl vs tap position in rheostat mode for 10k ? (w) figure 8. inl vs tap position in rheostat mode for 10k ? (w) typical performance curves (continued) dnl (lsb) -0.2 -0.1 0 0.1 0.2 0 20406080100120 tap position (decimal) t = +25c v cc = 5.5v v cc = 2.7v -0.2 -0.1 0 0.1 0.2 0 20 40 60 80 100 120 tap position (decimal) inl (lsb) t = +25c v cc = 5.5v v cc = 2.7v -0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 -40 -20 0 20 40 60 80 100 120 temperature (c) zs error (lsb) v cc = 5.5v v cc = 2.7v 50k 10k -1.5 -1.2 -0.9 -0.6 -0.3 0.0 -40 -20 0 20 40 60 80 100 120 temperature (oc) zs error (lsb) v cc = 5.5v v cc = 2.7v 50k 10k -0.6 -0.4 -0.2 0 0.2 0.4 16 36 56 76 96 116 tap position (decimal) dnl (lsb) t = +25c v cc = 2.7v v cc = 5.5v -0.6 -0.4 -0.2 0 0.2 0.4 16 36 56 76 96 116 tap position (decimal) inl (lsb) t = +25c v cc = 2.7v v cc = 5.5v isl22326
10 fn6176.3 september 9, 2015 figure 9. end to end r total % change vs temperature figure 10. tc for voltage divider mode in ppm figure 11. tc for rheostat mode in ppm figure 12. frequency respon se (2.6mhz) figure 13. midscale glitch, code 3f h to 40h figure 14. large signa l settling time typical performance curves (continued) -1.0 -0.5 0.0 0.5 1.0 -40 -20 0 20 40 60 80 100 120 temperature (oc) end to end r total change (%) 50k 10k v cc = 5.5v v cc = 2.7v 0 15 30 45 60 75 90 105 16 36 56 76 96 tap position (decimal) tcv (ppm/c) 50k 10k tcr (ppm/c) 0 50 100 150 200 250 300 16 36 56 76 96 tap position (decimal) 50k 10k output input wiper at mid point (position 40h) r total = 9.5k ? ??? ???? ???? ??? ??? ???? ???? isl22326
11 fn6176.3 september 9, 2015 pin descriptions potentiometers pins rhi and rli (i = 0, 1) the high (rhi) and low (rli) terminals of the isl22326 are equivalent to the fixed terminals of a mechanical potentiometer . rhi and rli are referenced to t he relative position of the wipe r and not the voltage pot ential on the termina ls. with wri set to 127 decimal, the wiper will be cl osest to rhi, and with the wri set to 0, the wiper i s closest to rli. rwi (i = 0,1) rwi is the wiper terminal and is equivalent to the movable terminal of a mechanical potenti ometer. the position of the wiper within the array is det ermined by the wri register. shdn the shdn pin forces the resistor to end-to-end open circuit condition on rhi and shor ts rwi to rli. when shdn is returned to logic high, the prev ious latch settings put rwi at the same resistance setting pr ior to shutdown. this pin is logically anded with shdn bit in acr register. i 2 c interface is still available in shutdown mode and all registers are accessible. this pin must remain high for normal operation. bus interface pins serial data input/output (sda) the sda is a bidirectional seri al data input/output pin for i 2 c interface. it receives device address, operation code, wiper address and data from an i 2 c external master device at the rising edge of the serial clock scl, and it shifts out data aft er each falling edge of the serial clock. sda requires an external pull-up resistor, since it is an open drain input/output. serial clock (scl) this is the serial c lock input of the i 2 c serial interface. scl requires an external pull-up resistor, since it is an open drai n input. device address (a2 - a0) the address inputs are used to set the least significant 3 bits of the 7-bit i 2 c interface slave address. a match in the slave address serial data stream m ust match with the address input pins in order to initi ate communication with the isl22326. a maximum of 8 is l22326 devices may occupy the i 2 c serial bus. principles of operation the isl22326 is an integrated circuit incorporating two dcps with their associated reg isters, non-volatile memory and an i 2 c serial interface providing direct communication between a host and t he potentiometers and memory. the resistor arrays are compris ed of individual resistors connected in series. at either end of the arra y and between each resistor is an electronic switch that transfers the potential at that point to the wiper. the electronic switches on the device operat e in a make before break mode when the w iper changes tap positions. when the device is powered dow n, the last value stored in ivri will be maintained in the non-volatile memory. when power is restored, the contents of the ivri are recalled and loaded into the corresponding wri to set the wipers to the initial value. dcp description each dcp is implemented with a combination of resistor elements and cmos switches. the physical ends of each dcp are equivalent to the fix ed terminals of a mechanical potentiometer (rh and rl pins). the rw pin of each dcp is connected to i ntermediate nodes, and is equivalent to the wiper terminal of a mechanica l potentiometer. the position of the wiper terminal within the dcp is controlled by volatile wiper register (wr). each dcp has its own wr. when the wr of a dcp contains all zero es (wr[6:0]= 00h), its wiper terminal (rw) is closest to its low terminal (rl). when the wr register of a dcp contains all ones (wr[6:0] = 7fh), its wiper terminal (rw) is closest to its high terminal (rh). as the value of the wr increases f rom all zeroes (0) to all ones (127 decimal), the wiper m oves monotonically from the position closest to rl to the closest to rh. at the same time, the resistance between rw and rl increases monotonically, while the resistance bet ween rh and rw decreases monotonically. while the isl22326 is being power ed up, all wrs are reset to 40h (64 decimal), which locat es rw roughly at the center between rl and rh. after the power supply voltage becomes large enough for re liable non-volatile memory reading, all wrs will be rel oad with the valu e stored in corresponding non-volatile initi al value registers (ivrs). the wrs can be rea d or written to directly using the i 2 c serial interface as described i n the following sections. the i 2 c interface address byte has to be set to 00h or 01h to access the wr of dcp0 o r dcp1 respectively. memory description the isl22326 contains seven non-volatile and three volatile 8-bit registers. memory map o f isl22326 is on table 1. the two non-volatile registers (iv ri) at address 0 and 1, contain initial wiper value and volatile registers (wri) contain curren t wiper position. in addition, five non-volatile general purpose registers from address 2 to address 6 are available. rl rw rh figure 15. dcp connect ion in shutdown mode isl22326
12 fn6176.3 september 9, 2015 the non-volatile ivri and volatile wri registers are accessible with the same address. the access control register ( acr) contains information and control bits described in t able 2. the vol bit at access control register (acr[7]) dete rmines whether the access is to wiper registers wri or ini tial value registers ivri. if vol bit is 0, the non-volatile ivri registers are accessible . if vol bit is 1, only the volatile wri are accessible. note, value is written to ivri register also is written to the correspondin g wri. the default value of this bit is 0. the shdn bit (acr[6]) disables or enables shutdown mode. this bit is logica lly anded with shdn pin. when this bit is 0, dcp is in shutdown mode. default value of shdn bit is 1. the wip bit (a cr[5]) is read only bi t. it indicates that non-volatile write operation is in progress. it is impossible t o write to the ivri, wri or acr while wip bit is 1. shutdown mode the device can be put in shutdown mode either by pulling the shdn pin to gnd or setting the shdn bit in the acr register to 0. the truth table for s hutdown mode is in table 3. i 2 c serial interface the isl22326 supports an i 2 c bidirectional bus oriented protocol. the pr otocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlli ng the transfer is a master and the device being controlled is the slave. the master always initiates data transfers and provides the clock for both transmit and receive operatio ns. therefore, the isl22326 operates as a slave device in all applications. all communication over the i 2 c interface is conducted by sending the msb of eac h byte of data first. protocol conventions data states on the sda lin e must change only during scl low periods. sda state cha nges during scl high are reserved for indicating st art and stop conditions (see figure 16). on power-up of the isl22326, the sda pin is in the input mode. all i 2 c interface operations m ust begin with a start condition, which is a high to l ow transition of sda while scl is high. the isl22326 continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition is met (see figure 16). a start condition is ignored during the power-up of the device. all i 2 c interface operations must be terminated by a stop condition, which is a low to h igh transition of sda while scl is high (see figure 16). a stop condition at the end of a read operation, or at the end of a write operation places the device in its standby mode. an ack, acknowledge, is a so ftware convention used to indicate a successful data tran sfer. the transmitting device, either master or slave, re leases the sda bus after transmitting eight bits. duri ng the ninth cl ock cycle, the receiver pulls the sda line low to acknowledge the reception of the eight bit s of data (see figure 17). the isl22326 responds with an ack after recognition of a start condition followed by a v alid identificat ion byte, and once again after succe ssful receipt of an address byte. the isl22326 also responds with an ack after receiving a data byte of a write ope ration. the master must respond with an ack after receiving a data byte of a read operation. a valid identification byte con tains 1010 as the four msbs, and the following three bits matching the logic values present at pins a2, a1, and a0. the lsb is the read/write bit. its value is 1 for a read operation, and 0 for a write operatio n (see table 4). table 4. identification byte format table 1. memory map address non-volatile volatile 8 acr 7 reserved 6 5 4 3 2 general purpose general purpose general purpose general purpose general purpose not available not available not available not available not available 1 0 ivr1 ivr0 wr1 wr0 table 2. access control register (acr) vol shdn wip 00000 table 3. shdn pin shdn bit mode high 1 normal operation low 1 shutdown high 0 shutdown low 0 shutdown 1010a2a1a0r/w (msb) (lsb) logic values at pins a2, a1, and a0 respectively isl22326
13 fn6176.3 september 9, 2015 sda scl start data data stop stable change data stable figure 16. valid data changes, start and stop conditions sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high impedance high impedance figure 17. acknowledge response from receiver s t a r t s t o p identification byte address byte data byte a c k signals from the master signals from the slave a c k 1 0 1 00 a c k write signal at sda 0000 a0 a1 a2 0 figure 18. byte write sequence signals from the master signals from the slave signal at sda s t a r t identification byte with r/w = 0 address byte a c k a c k 10 1 00 s t o p a c k 1 1 1 00 identification byte with r/w = 1 a c k s t a r t last read data byte first read data byte a c k 0 000 a0 a1 a2 a0 a1 a2 figure 19. read sequence a c k isl22326
14 fn6176.3 september 9, 2015 write operation a write operation requires a start condition, followed by a valid identification byte, a valid addre ss byte, a data byte, and a stop condition. after each of the three bytes, the isl22326 responds with an ack . at this time, the device enters its standby state (see figure 18). the device can receive more than one byte of data by auto incrementing the address after each received byt e. note after reaching the address 08h, the internal point er rolls over to address 00h. the non-volatile write cycle st arts after stop condition is determined and it requires up t o 20ms delay for the next non-volatile write. thus, non- volatile registers must be written individually. read operation a read operation consist of a three byte instruction followed by one or more data bytes (s ee figure 19). the master initiates the operation issuing the following sequence: a start, the identificatio n byte with the r/w bit set to 0, an address byte, a second start , and a second identification byte with the r/w bit set to 1. after each of the three bytes, the isl22326 respon ds with an ack. then the isl22326 transmits data bytes as long a s the master responds with an ack during the scl cycle following the eighth bit of each byte. the master terminates the read operation (issuing a ack and a stop condition) following the last bit of the last data byte (see figure 19). the data bytes are from the registers indicated by an internal pointer. this pointer initial value is determined by t he address byte in the read operation instruction, and increments by one during transmission of each data byte. after reaching the memory locat ion 08h, the pointer rolls over to 00h, and the device c ontinues to output data for each ack received. in order to read back the non-volatile ivr, it is recommended that the application r eads the acr first to verify the wip bit is 0. if the wip bit ( acr[5]) is not 0, the host should repeat its reading sequence again. isl22326
15 all intersil u.s. products are m anufactured, assembled and test ed utilizing iso9001 quality systems. intersil corporations quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products , see www.intersil.com fn6176.3 september 9, 2015 about intersil intersil corporation is a leading provider of innovative power management and precision analog solutions. the company's produc ts address some of the largest marke ts within the industrial and i nfrastructure, mobile computing and high-end consumer markets. for the most updated datasheet, application no tes, related documentation and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggesti ons for improving this datashe et by visiting www.intersil.com/ask . reliability reports are also a vailable from our website at www.intersil.com/support. revision history the revision history provided is for informational purposes onl y and is believed to be accura te, but not warranted. please go to the web to make sure that you have the latest revision. date revision change september 9, 2015 fn6176.3 updated ordering information table on page 2. added revision history and about intersil sections. updated package outline drawing l16.4x4a to the latest revision . -revision 2 to revision 3 changes - updated to new pod format b y removing table listing dimensions and moving dimensions onto drawi ng. added typical recommended land pattern. removed package option. updated package outline drawing m14.173 to the latest revision. -revision 2 to revision 3 changes - updated drawing to remove t able and added land pattern. isl22326
16 fn6176.3 september 9, 2015 isl22326 package outline drawing l16.4x4a 16 lead quad flat no-lead plastic package rev 3, 03/15 notes: 1. dimensions are in millimeters. dimensions in ( ) for reference only. 2. dimensioning and tolerancing conform to asme y14.5m-1994. 3. unless otherwise specified , tolerance: decimal 0.05 4. dimension applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. tiebar shown (if present) is a non-functional feature. 6. the configuration of the pin #1 identifier is optional, but m ust be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. top view index area (4x) 0.15 pin 1 6 4.00 4.00 a b see typical recommended land pattern 0.20 ref +0.03/-0.02 detail "x" c 5 side view bottom view 0.08 c c seating 0.10 c +0.05 pin #1 5 8 4 0.10 c m 12 9 4 0.50 12x 13 4x 1.50 16 1 6 a b ( 2.40) (12x 0.50) (16x 0.25) (3.8 typ) -0.07 0.25 0.900.10 2.40 16x 0.400.01 (16x 0.60) index area 2.40 detail "x" plane
17 fn6176.3 september 9, 2015 isl22326 package outline drawing m14.173 14 lead thin shrink small outline package (tssop) rev 3, 10/09 detail "x" side view typical recommended land pattern top view b a 17 8 14 c plane seating 0.10 c 0.10 c b a h pin #1 i.d. mark 5.00 0.10 4.40 0.10 0.25 +0.05/-0.06 6.40 0.20 c b a 0.05 0-8 gauge plane see 0.90 +0.15/-0.10 0.60 0.15 0.09-0.20 5 2 3 1 3 1.00 ref 0.65 1.20 max 0.25 0.05 min 0.15 max (1.45) (5.65) (0.65 typ) (0.35 typ) detail "x" 1. dimension does not include mold flash, protrusions or gate b urrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. dimension does not include interlead flash or protrusion. i nterlead flash or protrusion shall not exceed 0.25 per side. 3. dimensions are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m-1994. 5. dimension does not include dambar protrusion. allowable prot rusion shall be 0.80mm total in excess of dimension at maximum materia l condition. minimum space between protrusion and adjacent lead is 0.07mm. 6. dimension in ( ) are for reference only. 7. conforms to jedec mo-153, variation ab-1. notes: end view

▲Up To Search▲

Price & Availability of ISL22326WFV14Z

	To Download ISL22326WFV14Z Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .